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W40C06A
Six Outputs
Features
* * * * * * Six skew-controlled CMOS outputs with enables Low output impedance, high current output buffers Each output can drive two 50 (or higher) clock lines 3.3V operation DC to 100-MHz operation Controlled output rate slew reduces EMI and output ringing * Ideal for PCI or CPU clock distribution * Low power CMOS design available in: -- 16-pin SSOP (Shrink Small Outline Package)
Key Specifications
Supply Voltages:........................................ VCC = 3.3V 10% or 5.0V10% Operating Temperature:.................................... 0C to +70C Output Frequency: ......................................... DC to 100 MHz Skew Output: ........................................ <400 ps rising edges <500 ps falling edges Output Drive Current: .......................................... 48 mA max Output Impedance: ............................................................ 5 Output Rise/Fall Edge Rate: .............................1 to 4 volts/ns Output Duty Cycle: .................................. 40/65% worst case
Table 1. Output Enable Selection (-14) W40C06A-14 CKEN 0 1 Q0 Active Active Q1:5 Low Active
Block Diagram
Q0 TCLK
Pin Configuration
Q2 Q3 Q4
W40C06A-14
Input Control
Q1
NC CKEN GND Q0 VDD Q1 GND Q2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
NC TCLK Q3 VDD Q4 GND Q5 VDD
CKEN
Synchronization Logic
Q5
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 September 28, 1999, rev. **
W40C06A
Pin Definitions
Pin Name Q0:5 VDD GND CKEN TCLK NC Pin No. 4, 6, 8, 10, 12, 14 5, 9, 13 3, 7, 11 2 15 1, 16 Pin Type O P G I I NC Pin Description Buffered Clock Outputs: Six skew controlled CMOS clock outputs. Power Connection: Power supply for core logic and output buffers. Connected to a 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane. Clock Enable: Provide Start/Stop control of buffer outputs refer to Table 1. Clock Input: External reference frequency input. No Connection: These pins should remain unconnected. source impedance is typically controlled but is not practical to control load impedance. Clock source impedance is matched to the transmission line by using series termination; this involves the addition of a series termination resistor between the output pin and transmission line to, in effect, raise the output buffer impedance to match the line. For example, if the clock output buffer impedance is 30 and the transmission line impedance is 50, a 20 termination resistor connected between the clock output and transmission line will match the two (the clock buffer impedance becomes 50). The end of the transmission line is usually "open" with the only load being the typically high-resistance capacitive load of the logic input on the device being clocked. This condition causes a reflection to be sent back to the source. If the source is properly matched to line (through series termination), this reflection will be absorbed (a poorly matched source will re-reflect the pulse edge which can cause waveform distortion by mixing a reflected edge with a new clock pulse edge). It is interesting to note that when a new clock edge is first driven into the transmission line, the voltage level at the input of the line is only one-half the final signal amplitude, assuming a properly matched line. This edge remains at half amplitude for the time it takes for the edge to reach the end of the line and back. The edge travels down the line at a speed of about 0.2 ns per inch of transmission, so for a five-inch line this round-trip takes about 2.0 ns. During that time, the clock source dissipates power at the rate of (VDD/2)2/R, where R is the sum resistance of the output buffer and series termination resistor (this assumes the case of a CMOS output driver, as used in the W40C06A, where the clock signal amplitude is equal to VDD). W40C06A Clock Driver Advantages Low Output Impedance The typical CMOS clock buffer device has an output impedance of around 50. This means that a typical 60 transmission line can be properly series terminated with a 10 matching resistor. However, two 60 transmission lines could not be driven with series termination (to maintain good waveform integrity) since this presents a 30 load to the buffer. The W40C06A exhibits a 5 typical buffer output impedance. The main advantage of the low W40C06A output impedance is that one output can drive more than one transmission line while maintaining proper series termination. For example, if
General Overview
The W40C06A is a six-output, low-skew clock buffer ideally suited for PCI, CPU, and other system clock applications. Each high-current, low-impedance output is specifically designed to drive up to two impedance-controlled signal lines. Controlled output rise/fall times further help to provide good signal characteristics. The W40C06A is ideal for clock signal distribution in skew sensitive applications such as Pentium(R) processor or PCI applications. W40C06A-14 has an enable input pin (see Table 1) that starts and stops the clock outputs without producing short cycles. Functional Description The W40C06A enable pin provides start/stop control of buffer outputs Q0 through Q5. Refer to Table 1, "Output Enable Selection," for decoding. Active (enabled) outputs are in phase with TCLK but are phase delayed by several nanoseconds. Low (disabled) outputs are held at logic LOW. Synchronization Logic Output Control To prevent output "short cycling," internal synchronization logic is used to ensure complete clocks cycles. This is true for both output enable or disable. Upon enabling an output, there is a maximum latency of four clock cycles, assuming the crystal oscillator is active. Clock Transmission Lines in System Applications With the increase in system clock frequencies, transmission line theory is commonly being applied to the design of clock distribution lines. High-speed logic systems typically require tight skew control between clock lines, which means that the clock signal must have short rise/fall times to overcome the effect of noise. Short rise/fall times may create other problems such as signal overshoot/undershoot and signal reflections which may result in distorting the signal at the load end. These problems must be avoided since they create unwanted clock skew. Reflections and signal overshoot/undershoot can be controlled by designing clock distribution traces as transmission lines. A transmission line accepts and delivers a clock signal without distortion or reflections if its impedance is matched to the line source and load. In system clock line implementation,
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W40C06A
driving two 50 lines, the W40C06A buffer output resistance (as seen by each line) will be about 10, therefore each line can be series terminated with a 40 resistor. Other advantages are also gained by the W40C06A buffer output impedance being much less than the series termination resistor value. First, output buffer impedance variation will have less effect on total source impedance. A CMOS output buffer can vary as much as 20% with changes in process and operating conditions, while variation of the termination resistor is typically less than 5%. Source impedance (with less variation) results in better signal integrity. Second, more power will be dissipated by the series termination resistor than by the output buffer. This can be important when driving many long transmission lines; the termination resistors are less affected by heating than are CMOS buffer devices. Controlled Output Rise and Fall Time The W40C06A incorporates internal clock edge rise/fall time control to further improve clock integrity. Rise/fall times that are too fast cause excessive signal overshoot/undershoot due to interactions between the high device impulse current and power supply inductance caused by the device packaging. Rise/fall times that are too slow make it difficult to meet the system clock skew requirement, especially in the presence of system noise.
3
W40C06A
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 Unit V C C C
3.3V DC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V10%
Parameter IDD IDD VIL VIH VOL VOH IIL IIH CIN CL Description Supply Current Standby Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Input Capacitance Load Capacitance Test Condition Note 1 CKEN = 0 VDD = 3.3V VDD = 3.3V IOL = 48 mA, VDD = 3.3V IOH = -48 mA, VDD = 3.3V VIN = 0V VIN = VDD Except pin TCLK Pin TCLK 2.4 -2.5 -2.5 5 6 2.5 2.5 9 2.0 0.4 Min Typ 50 7 Max 60 12 0.8 Unit mA A V V V V A A pF pF
3.3V AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V10%[2]
Parameter fIN ZOUT tON tOFF tEN tDIS tR tF tSR tSF tD tJA Description Input Frequency Active Output Source Impedance Start-up Time to First Clock Cycle Turnoff Time to Standby State Output Enable Time Output Disable Time Output Rise Edge Rate Output Fall Edge Rate Output Skew Rising Edges Output Skew Falling Edges Duty Cycle Jitter, Absolute Outputs loaded Oscillator initially off Oscillator initially running Oscillator already running Oscillator stays running Outputs loaded Outputs loaded Same package Same package 45 1 1 200 200 50 Test Condition TTL clock into TCLK Min 0 5.0 5 4 4 4 4 4 400 500 55 300 Typ Max 100 Unit[3] MHz ms cycles cycles cycles V/ns V/ns ps ps % ps
Notes: 1. W40C06A with no output loading. 2. All AC tests are performed with 20-pF load on each clock output unless otherwise specified. Threshold voltage for timing measurements is 1.5V. 3. Unit "cycles" implies input clock cycles.
4
W40C06A
Applications Information
Series Termination Resistors R S1, RS2, and RS3 in Figure 3 are series termination resistors used for matching the impedance of the output buffer to the impedance of the transmission line. This is accomplished by sizing the series termination resistor value so that when added to the output buffer impedance this value matches the transmission line impedance. The resistors should be placed as close to the output pins as possible. In Figure 3, output Q5 drives one line and Q3 drives two lines (for diagrammatic simplicity not all device pins are connected). As stated previously, the W40C06A exhibits a 5 buffer impedVOL - 3.3V Supply 3.5 3.0 2.5 Voltage (V) 2.0 1.5 1.0 0.5 0.0 0 100 200 300 400 Current, Pull-Up (mA) Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 100 200 300 400 Current, Pull-Down (mA)
ance when driving one 50 transmission line and appears to have an 8-12 impedance when driving two transmission lines as viewed from each line). Assuming this transmission line impedance, this means that R S1 needs to be 45 and RS2, R S3 need to be 40 each. In order to drive the typical capacitive load of a CMOS input, typical transmission line impedance is 50-100. Power Supply Connections GND pins should be connected directly to the ground plane. Each VDD pin should be connected to the power plane and should include a decoupling capacitor.
VOH - 3.3V Supply
Figure 1. Typical DC Output V/I Characteristics
tH
tS
tH
tS
NC
1 2
16 15
NC TCLK Q3 VDD Q4 GND Q5 VDD
RS3 RS2 RS1
TCLK
(input)
CKEN GND Q0 VDD Q1
W40C06A-14
CKEN
(input)
3 4 5 6 7 8
14 13 12 11 10 9
Q1:5
(outputs)
Figure 2. CKEN Timing Requirements
GND Q2
Figure 3. Application Diagram
Ordering Information
Ordering Code W40C06A Freq. Mask Code -14 Package Name H Package Type 16-pin Plastic SSOP (150-mil)
Pentium is a registered trademark of Intel Corporation. Document #: 30-00810
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W40C06A
Package Diagram
16-Pin Shrink Small Outline Package (TSSOP, 0.150 inch)
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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